The present invention relates to the field of memory circuits, and in particular to a hybrid decoder and scan data I/O scheme for memory circuits.
In order to extract data from a digital memory array, for example, often a wide data register is provided, coupled between the memory array and the input/output (I/O) port. The wide data register may comprise a series of cells with the individual cells coupled to respective bitlines of the array. Then, a selected row of data from the array can be transferred to the data register, and selected data from that row can be transferred from the corresponding register cells to the I/O port. Two methods have been used in the past to extract the selected data from the wide data register, one based on address decoding and the other based on scan shifting of the data register.
In the address decoding method, a connection is made to each register cell with a decoder to select and transfer the data stored in the selected data register cell(s) to a data bus. This scheme has the advantages of fast and random access to data in the register. The disadvantages are that each register cell requires a decoder and transfer device, and that an address bus (true and compliment) must be routed to each of the register cells. In a memory circuit in which integrated circuit space is important, the relatively large circuit area which is required by the decoding/transfer circuits and bus can be particularly disadvantageous.
The scan shifting method for wide data register access requires that the register cells be configured into a scan chain. Then, the data in the register is serially shifted into or out of the register at the rate set by the scan clock. The advantages of this method are simple I/O and clocking (2 wires, data I/O and scan clock), high speed burst rate (data I/O moves at the scan clock rate), and simple physical layout. However, this method has the disadvantage that a long latency may be involved in serially shifting data through the register until the data of interest exits the chain of scan register cells. The latency depends upon where the data of interest is positioned in the shift register relative to the I/O port.
In accordance with the principles of the present invention, there is provided a data input/output circuit which has a data register circuit and an I/O control circuit. The data register circuit comprises a sequence of shift register blocks. Each shift register block has at least one register cell, a data shift input, a data shift output and a shift clock input. The data shift inputs and outputs of the shift register blocks are coupled to pass data through the register circuit in sequence according to signals at the shift clock input. The couplings between data shift inputs and outputs form data access nodes. The I/O control circuit includes a plurality of transmission gate circuits coupling the respective data access nodes to a data input/output port. The I/O control circuit also includes selection circuitry coupled to the transmission gate circuits for selecting one of the transmission gate circuits on the basis of input from an address bus, so as to enable data to pass between the data register circuit and the input/output port through the selected transmission gate.
The data register circuit preferably includes a parallel data input/output path, for reading data from and/or writing data to the register cells of the data register circuit. In one form of the invention, the parallel data input/output path is coupled to a memory array, such that respective bitlines of the memory array are coupled to respective register cells of the data register circuit.
Each shift register block preferably comprises a plurality of register cells coupled in a chain to enable shifting of data therein through the plurality of cells from a first register cell having the data shift input to a second register cell having the data shift output. In the preferred form of the invention, each of the shift register blocks has an equal number of register cells.
In accordance with the present invention, there is also provided a method for data transfer which involves a data register having a chain of shift registers. Each of the shift registers has at least one register cell, a data shift input, a data shift output and a shift clock input. The data shift inputs and outputs of the shift registers are coupled to pass data through the data register according to signals at the shift clock input. The couplings between data shift inputs and outputs of the shift registers form data access nodes. In the data transfer method, one of the data access nodes is selected according to input on an address bus. Then, data is transferred into or out of the data register through the selected data access node by shifting data in the data register using the shift clock input.
Preferably, the data transfer method includes parallel input or output of data to or from the register cells of the data register. The parallel data transfer may be between the data register and a memory array, for example. The data can be transferred in parallel fashion between the data register and a memory array by coupling respective register cells to respective bitlines of the memory array. Magnetic random access memory (MRAM) circuits are particularly well suited to the characteristics of the data input/output circuit and method of the present invention, in view of the very small memory cell size, for example, which makes possible large memory arrays with consequently large I/O data registers.
To provide output transfer of data from a memory array, for example, selected data is provided by parallel input to the data register from an external data source, and at least a portion of the selected data is serially output through the selected data access node by shifting data in the data register using the shift clock input.
To provide input transfer of data to a memory array, for example, selected data is serially input to the data register through the selected data access node by shifting data in the data register using said shift clock input, and the selected data is then transferred by parallel output from the data register to the memory array.
Embodiments of this invention provide a solution to the serial I/O latency problem associated with scan chain shift registers while maintaining character of the serial I/O and high burst data rates offered by scan shift registers.